Integrated circuit designs for high speed signal processing

ABSTRACT

A method of designing an electronic circuit system with multiple CMOS transistors is presented. With this method, the circuit parameters of the various CMOS transistors as well as the passive electrical components of the individual functional building blocks of the circuit system are systematically adjusted to minimize the many deteriorating effects resulting from system-level interactions among these functional building blocks. In one embodiment, the method is applied to a CMOS IC (Integrated Circuit) that is a Divide-by-16 divider where the functional building blocks are four Divide-by-2 dividers. The high quality of the resulting output signals from each divider stage is graphically presented. In another embodiment, the method is applied to a CMOS IC that is a Bang Bang Phase Detector where the functional building blocks are three Master Slave D-Type Flip Flops. The high quality of the resulting output signal is also graphically presented.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation-in-part application of a prior application Ser. No. 09/947,643, filed Sep. 5, 2001 by the same inventors, now pending (“Zhang Ser. No. 09/947,643 application”) and of a prior application entitled “A 2-Level Series-Gated CML-Based Circuit With Inductive Components For Optical Communication”, filed Apr. 22, 2002 by the same inventors, now pending (the “Zhang Apr. 30, 2002 application”).

BACKGROUND OF THE INVENTION

[0002] The present invention relates generally to the field of data communication. More particularity, the present invention concerns a generic design methodology of a new family of Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits (IC). Thus, its direct applications include a variety of subsystem and system functions such as Master Slave D-type Flip Flop (MS-DFF), Divider, Bang Bang Phase Detector (BBPD), Frequency Detection (FD), Phase and Frequency Detection (PFD), Voltage Controlled Oscillator (VCO) and Phase Locked Loop (PLL) in an optical switch IC for data communication. Optical Fiber has been used in voice and data communication for some time now due to its high bandwidth and excellent signal quality resulting from its immunity to electromagnetic interference. The inherent optical data rate from a modulated single-mode laser beam travelling through an optical fiber is expected to well exceed 1000 Gbit/sec.

[0003] However, short of a completely optical communication system, the practically realizable bandwidth of fiber optical communication systems has been limited by the need of signal conversion between optical and electrical domain and the associated electronics hardware. With the usage of CMOS ICs, the advantages of low manufacturing cost, low operating power consumption, low supply voltage requirement and fairly good circuit density are realized while achieving a moderate speed capability. To fully realize the speed capability of CMOS IC at the circuit system level with good output signal quality, Zhang application Ser. No. 09/947,643 taught a method of systematically adjusting an Electrically Equivalent Channel Geometry (EECG) of all the individual CMOS transistors within each of the otherwise topologically similar building blocks of a circuit system consisting of CMOS transistors and resistors. Using this method, a maximum operating clock frequency of approximately 12 GHz is realizable when the IC is implemented with a 0.18 μm CMOS Silicon wafer process. However, Zhang application Apr. 22, 2002 taught the inclusion of inductive components into a fundamental building block of 2-level series-gated Current Mode Logic (CML)-based Field Effect Transistor (FET) circuit for an electronic circuit system for optical communication to achieve of a higher load-driving capacity under a much higher operating frequency of up to 50 GHz.

[0004] Therefore, the present invention aims to generalize the method of Zhang application Ser. No. 09/947,643 to include resistive and inductive circuit components into a CMOS IC system to reach a much higher operating clock frequency while maintaining good output signal quality.

SUMMARY OF THE INVENTION

[0005] The present invention is directed to a new family of high speed CMOS ICs including both resistive and inductive circuit components and a corresponding generic design methodology.

[0006] The first objective of this invention is to achieve a generic design methodology for a family of CMOS ICs including, in addition to the active MOS transistors, both resistive and inductive circuit components while maintaining good output signal quality.

[0007] Other objectives, together with the foregoing are attained in the exercise of the invention in the following description and resulting in the embodiment illustrated in the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

[0008] The current invention will be better understood and the nature of the objectives set forth above will become apparent when consideration is given to the following detailed description of the preferred embodiments. For clarity of explanation, the detailed description further makes reference to the attached drawings herein:

[0009]FIG. 1 shows a circuit architecture of a Divide-by-2 divider with current mode switching wherein both resistive and inductive circuit components are used;

[0010]FIG. 2A shows a logic functional block representation of the Divide-by-2 divider of FIG. 1;

[0011]FIG. 2B is a logic functional block diagram of a Divide-by-16 divider using the Divide-by-2 divider of FIG. 1;

[0012]FIG. 3 graphically details the quantitative design of the Divide-by-2 building blocks of the Divide-by-16 divider of FIG. 2B;

[0013]FIG. 4 through FIG. 7 successively depicts the output signal quality of the four Divide-by-2 dividers of the Divide-by-16 divider of FIG. 2B;

[0014]FIG. 8 shows a circuit architecture of an MS-DFF with current mode switching wherein both resistive and inductive circuit components are used;

[0015]FIG. 9A is a logic functional block representation of the MS-DFF of FIG. 8;

[0016]FIG. 9B is a logic functional block diagram of a typical BBPD using the MS-DFF of

[0017]FIG. 9A as its logic building block;

[0018]FIG. 10 graphically details the quantitative design of the MS-DFF building blocks of the BBPD of FIG. 9B; and

[0019]FIG. 11 depicts the output signal quality of the BBPD of FIG. 9B.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] In the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will become obvious to those skilled in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuitry have not been described in detail to avoid unnecessary obscuring aspects of the present invention. The detailed description is presented largely in terms of logic blocks and other symbolic representations that directly or indirectly resemble the operations of signal processing devices coupled to networks. These descriptions and representations are the means used by those experienced or skilled in the art to most effectively convey the substance of their work to others skilled in the art.

[0021] Reference herein to “one embodiment” or an “embodiment” means that a particular feature, structure, or characteristics described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Further, the order of blocks in process flowcharts or diagrams representing one or more embodiments of the invention do not inherently indicate any particular order nor imply any limitations of the invention.

[0022]FIG. 1 shows a circuit architecture of a Dividc-by-2 DIVIDER 1 with current mode switching. In this exemplary illustration the supply voltage AVDD is shown to be 1.8 Volt although other values could be used just as well, for example 2.5 Volt. AGND designates “analog ground” and VCS is a bias voltage applied to the gates of transistors Mc1 and Mc2 to set up a corresponding amount of source current flowing through them. Through DIVIDER 1, the frequency of a differential signal between CLK 11 and CLK 12 will be divided in half into the differential signal between Qh 17 and Qh 18. The differential signals Qh 17 and Qh 18 are then buffered through an Output Buffer 15, whose details are not shown here being non-essential to this invention, to become the differential signal between QI 13 and QI 14. The various active NMOS transistors arc designated as Mc1, Mc2, M1, M2, . . . , and M16. The four pull-up resistors are designated R3, R4, R13 and R14. Each of the two resistors RL1 and RL10 performs a simple function of voltage level shifting and are non-essential to the concept of this invention. However, as explained in Zhang application Apr. 22, 2002, the added inductive components L3, L4, L13 and L14, together with their formed transformers T134 and T134 of respective coupling coefficients K34 and K134, enable the DIVIDER 1 to achieve a higher operating frequency while providing a higher load-driving capacity. Furthermore, Zhang application Ser. No. 09/947,643 taught a method of systematically adjusting an Electrically Equivalent Channel Geometry (EECG) of all the individual CMOS transistors within each of the otherwise topologically similar building blocks of a circuit system comprising CMOS transistors and resistors. Therefore, the present invention proposes to adjust the functionally relevant electrical parameters of ALL the active and passive circuit components of the otherwise topologically similar building blocks of a circuit system comprising any active and any passive components. This will be presently illustrated with a first embodiment of a Divide-by-16 circuit system having four Divide-by-2 building blocks.

[0023]FIG. 2A shows a logic functional block representation of the Divide-by-2 divider of FIG. 1. FIG. 2B is a logic functional block diagram of a Divide-by-16 DIVIDER 60 using the Divide-by-2 divider from FIG. 2A as its logic building block. Specifically, the replicated logic building blocks are labeled as DIVIDER 20, DIVIDER 30, DIVIDER 40 and DIVIDER 50. For those skilled in the art, it can be easily seen that the frequency of INPUT CLOCK 21 gets divided by two (2) as differential signal QI−QI=DOUT1 at the output of DIVIDER 20. Likewise, the frequency of INPUT CLOCK 21 gets divided by four (4) as differential signal QI−QI=DOUT2 at the output of DIVIDER 30. The frequency of INPUT CLOCK 21 gets divided by eight (8) as differential signal QI−QI=DOUT3 at the output of DIVIDER 40. Finally, the frequency of INPUT CLOCK 21 gets divided by sixteen (16) as differential signal QI−QI=DOUT4 at the output of DIVIDER 50.

[0024] It is well known in the art that, at the IC-design level for a given wafer process, the conductance of an MOS transistor is primarily determined by the following parameter:

[0025] W/L, where W=channel width and L=channel length.

[0026] For convenience, the following parameter is defined:

[0027] Electrically Equivalent Channel Geometry (EECG)=W/L.

[0028] To conveniently describe the functionally relevant and adjustable electrical parameters of all the circuit components of a building block within a circuit system, an Electrically Equivalent Component Parameter (EECP) is defined as follows:

[0029] EECP of a resistor=its resistance value;

[0030] EECP of an inductive component=its inductance value;

[0031] EECP of a transformer formed with coupled inductive components=a vector quantity consisting of the individual inductance value and the coupling coefficient between the inductive components;

[0032] EECP of a capacitive component=its capacitance value; and

[0033] EECP of an MOS transistor=its EECG.

[0034] Given the above definition and as a result of the present invention, the detailed quantitative designs of the four Divide-by-2 building blocks of DIVIDER 20, DIVIDER 30, DIVIDER 40 and DIVIDER 50 of the Divide-by-16 DIVIDER 60 are arrived and shown in the following TABLE-1A, TABLE-1B, TABLE-1C and TABLE-1D: TABLE 1A Design of EECP for DIVIDER 20 RATIO Component EECP Unit of EECP R3 25 Ohm 1.667 R4 25 Ohm 1.667 R13 15 Ohm 1.000 R14 15 Ohm 1.000 L3 250 Picohenry 16.667 L4 250 Picohenry 16.667 L13 180 Picohenry 12.000 L14 180 Picohenry 12.000 K34 0.5 dimensionless 0.033 K134 0.5 dimensionless 0.033 MC1 260 dimensionless 17.333 MC11 260 dimensionless 17.333 M1 160 dimensionless 10.667 M2 160 dimensionless 10.667 M11 160 dimensionless 10.667 M12 160 dimensionless 10.667 M3 120 dimensionless 8.000 M4 120 dimensionless 8.000 M5 170 dimensionless 11.333 M6 170 dimensionless 11.333 M13 140 dimensionless 9.333 M14 140 dimensionless 9.333 M15 170 dimensionless 11.333 M16 170 dimensionless 11.333

[0035] TABLE 1B Design of EECP for DIVIDER 30 RATIO Component EECP Unit of EECP R3 90 Ohm 1.500 R4 90 Ohm 1.500 R13 60 Ohm 1.000 R14 60 Ohm 1.000 L3 850 Picohenry 14.167 L4 850 Picohenry 14.167 L13 750 Picohenry 12.500 L14 750 Picohenry 12.500 K34 0.5 dimensionless 0.008 K134 0.5 dimensionless 0.008 MC1 240 dimensionless 4.000 MC11 240 dimensionless 4.000 M1 120 dimensionless 2.000 M2 120 dimensionless 2.000 M11 120 dimensionless 2.000 M12 120 dimensionless 2.000 M3 150 dimensionless 2.500 M4 150 dimensionless 2.500 M5 180 dimensionless 3.000 M6 180 dimensionless 3.000 M13 140 dimensionless 2.333 M14 140 dimensionless 2.333 M15 160 dimensionless 2.667 M16 160 dimensionless 2.667

[0036] TABLE 1C Design of EECP for DIVIDER 40 RATIO Component EECP Unit of EECP R3 200 Ohm 0.667 R4 200 Ohm 0.667 R13 300 Ohm 1.000 R14 300 Ohm 1.000 L3 0 Picohenry 0.000 L4 0 Picohenry 0.000 L13 0 Picohenry 0.000 L14 0 Picohenry 0.000 K34 0 dimensionless 0.000 K134 0 dimensionless 0.000 MC1 240 dimensionless 0.800 MC11 240 dimensionless 0.800 M1 100 dimensionless 0.333 M2 100 dimensionless 0.333 M11 100 dimensionless 0.333 M12 100 dimensionless 0.333 M3 80 dimensionless 0.267 M4 80 dimensionless 0.267 M5 90 dimensionless 0.300 M6 90 dimensionless 0.300 M13 80 dimensionless 0.267 M14 80 dimensionless 0.267 M15 90 dimensionless 0.300 M16 90 dimensionless 0.300

[0037] TABLE 1D Design of EECP for DIVIDER 50 RATIO Component EECP Unit of EECP R3 250 Ohm 1.000 R4 250 Ohm 1.000 R13 250 Ohm 1.000 R14 250 Ohm 1.000 L3 0 Picohenry 0.000 L4 0 Picohenry 0.000 L13 0 Picohenry 0.000 L14 0 Picohenry 0.000 K34 0 dimensionless 0.000 K134 0 dimensionless 0.000 MC1 180 dimensionless 0.720 MC11 180 dimensionless 0.720 M1 80 dimensionless 0.320 M2 80 dimensionless 0.320 M11 80 dimensionless 0.320 M12 80 dimensionless 0.320 M3 100 dimensionless 0.400 M4 100 dimensionless 0.400 M5 150 dimensionless 0.600 M6 150 dimensionless 0.600 M13 100 dimensionless 0.400 M14 100 dimensionless 0.400 M15 150 dimensionless 0.600 M16 150 dimensionless 0.600

[0038] The following examples from TABLE-1A, the design of EECP for the DIVIDER 20, are given to further clarify the various table entries:

[0039] Design of EECP:

[0040] Resistor R3=25 Ohm

[0041] Resistor R14=15 Ohm

[0042] Inductive component L13=180 Picohenry (10⁻¹² henry)

[0043] Inductive component L14=180 Picohenry (10⁻¹² henry)

[0044] K134=coupling coefficient between L13 and L14=0.5 (dimensionless)

[0045] Transistor Mc1 has an EECG of 260 (dimensionless)

[0046] Transistor M1 has an EECG of 160 (dimensionless)

[0047] Thus, the corresponding “RATIO of EECP” is given by:

[0048] 25:15:180:180:0.5:260:160=1.667:1.000:12.000:12.000:0.033:17.333:10.667

[0049] In arriving at the above RATIO of EECP, a choice of using the EECP of R14 as a common divisor is made. It is remarked that this choice is arbitrary for as long as the resulting RATIO of EECP falls within a convenient range for easy presentation of the inventive concept. However, for consistency of presentation, once this choice of R14 is made for a particular building block it is best to stick to the same choice for the calculation of RATIO of EECP for all the other building blocks of the circuit system. Notice also that while there is a general absence of EECP for a capacitive component in the above tables, for those skilled in the art, it should be understood that the adjustment of EECP for numerous capacitive components have already been implicitly included in the present invention. This is due to the presence of inherent capacitance components among the gate, the source, the drain and the bulk of any MOS transistor within a building block and the EECP of these capacitance components would vary according to the adjustment of EECG for each particular MOS transistor under consideration.

[0050] TABLE-1E summarizes a design overview of the Divide-by-16 DIVIDER 60 from the present invention. Notice that, among the four Divide-by-2 building blocks of DIV1 (DIVIDER 20), DIV2 (DIVIDER 30), DIV3 (DIVIDER 40) and DIV4 (DIVIDER 50), the four columns of “RATIO of EECP” are all different and they are further graphically illustrated in FIG. 3. The corresponding output waveforms, given an INPUT CLOCK 21 frequency of 50 GHz, from DIVIDER 20, DIVIDER 30, DIVIDER 40 and DIVIDER 50 are respectively shown in FIG. 4, FIG. 5, FIG. 6 and FIG. 7. Except for a slight signal distortion 65 from DIVIDER 50 (FIG. 7), the rest of the output waveforms (FIG. 4, FIG. 5 and FIG. 6) exhibit no visible distortion. TABLE 1E Overview of Design of EECP for DIVIDER 60 RATIO RATIO RATIO RATIO of EECP of EECP of EECP of EECP Component DIV1 DIV2 DIV3 DIV4 R3 1.667 1.500 0.667 1.000 R4 1.667 1.500 0.667 1.000 R13 1.000 1.000 1.000 1.000 R14 1.000 1.000 1.000 1.000 L3 16.667 14.167 0.000 0.000 L4 16.667 14.167 0.000 0.000 L13 12.000 12.500 0.000 0.000 L14 12.000 12.500 0.000 0.000 K34 0.033 0.008 0.000 0.000 K134 0.033 0.008 0.000 0.000 MC1 17.333 4.000 0.800 0.720 MC11 17.333 4.000 0.800 0.720 M1 10.667 2.000 0.333 0.320 M2 10.667 2.000 0.333 0.320 M11 10.667 2.000 0.333 0.320 M12 10.667 2.000 0.333 0.320 M3 8.000 2.500 0.267 0.400 M4 8.000 2.500 0.267 0.400 M5 11.333 3.000 0.300 0.600 M6 11.333 3.000 0.300 0.600 M13 9.333 2.333 0.267 0.400 M14 9.333 2.333 0.267 0.400 M15 11.333 2.667 0.300 0.600 M16 11.333 2.667 0.300 0.600

[0051] Another exemplary case of application of the current invention is illustrated from FIG. 8 to FIG. 9. FIG. 8 and FIG. 9A show a typical circuit architecture of an MS-DFF 70 with current mode switching and its associated logic functional block representation. In this exemplary case the supply voltage AVDD is shown to be 1.8 Volt although other values could be used just as well, for example 2.5 Volt. The input clock signals are CLK 71 and CLK 72. The input data signals are D 73 and D 74. The pre-output differential signals 76 a and 77 a are then buffered through an Output Buffer 75, whose details are not shown here being non-essential to this invention, to become the output differential signal pairs (Qh 76, Qh 77) and (QI 78, QI 79). The various active NMOS transistors are designated as Mc1, Mc2, M1, M2, . . . , and M16. The four pull-up resistors are designated R3, R4, R13 and R14. Like before, the added inductive components L3, L4, L13 and L14, together with their formed transformers T34 and T134 of respective coupling coefficients K34 and K134, expect to enable the MS-DFF 70 to achieve a higher operating frequency while providing a higher load-driving capacity. Similarly, the present invention proposes to adjust the EECPs of all the active and passive circuit components of the otherwise topologically similar building blocks of a circuit system comprising any active and any passive components. This will be presently illustrated with a second embodiment of a Bang Bang Phase Detector (BBPD) circuit system having three MS-DFF building blocks.

[0052]FIG. 9B is a logic functional block diagram of a typical BBPD 80 using the MS-DFF 70 from FIG. 9A as its logic building block. Specifically, the replicated logic building blocks are labeled as MS-DFF 81, MS-DFF 82 and MS-DFF 83. The input signals include VCO 85 and DATA-IN 86. The output signals include a PHASE 88 and PHASE 89. For those skilled in the art, it can be seen that the logic state of PHASE 88 and PHASE 89 will change according to the phase relationship of leading or lagging between the two input signals VCO 85 and DATA-IN 86. For convenience, the following differential signal is also defined:

ΔPHASE=PHASE−PHASE.

[0053] Like before, while using the same circuit architecture of an MS-DFF 70 with current mode switching as the building blocks, a system level design of BBPD 80 using the method of the present invention also yields a high level of output signal quality especially for high VCO frequency as in optical communications. This is illustrated, in a manner similar to the first exemplary case of DIVIDER 60, for a BBPD 80 of VCO 85 frequency=40 GHz and DATA-IN 86 date rate=41.66 Gbit/sec with TABLE-2A, TABLE-2B and TABLE-2C below: TABLE 2A Design of EECP for MS-DFF 81 RATIO Component EECP Unit of EECP R3 150 Ohm 1.000 R4 150 Ohm 1.000 R13 150 Ohm 1.000 R14 150 Ohm 1.000 L3 700 Picohenry 4.667 L4 700 Picohenry 4.667 L13 700 Picohenry 4.667 L14 700 Picohenry 4.667 K34 0.5 dimensionless 0.003 K134 0.5 dimensionless 0.003 MC1 260 dimensionless 1.733 MC11 260 dimensionless 1.733 M1 200 dimensionless 1.333 M2 200 dimensionless 1.333 M11 200 dimensionless 1.333 M12 200 dimensionless 1.333 M3 90 dimensionless 0.600 M4 90 dimensionless 0.600 M5 70 dimensionless 0.467 M6 70 dimensionless 0.467 M13 90 dimensionless 0.600 M14 90 dimensionless 0.600 M15 70 dimensionless 0.467 M16 70 dimensionless 0.467

[0054] TABLE 2B Design of EECP for MS-DFF 82 RATIO Component EECP Unit of EECP R3 150 Ohm 1.000 R4 150 Ohm 1.000 R13 150 Ohm 1.000 R14 150 Ohm 1.000 L3 500 Picohenry 3.333 L4 500 Picohenry 3.333 L13 500 Picohenry 3.333 L14 500 Picohenry 3.333 K34 0.5 dimensionless 0.003 K134 0.5 dimensionless 0.003 MC1 260 dimensionless 1.733 MC11 260 dimensionless 1.733 M1 200 dimensionless 1.333 M2 200 dimensionless 1.333 M11 200 dimensionless 1.333 M12 200 dimensionless 1.333 M3 70 dimensionless 0.467 M4 70 dimensionless 0.467 M5 90 dimensionless 0.600 M6 90 dimensionless 0.600 M13 70 dimensionless 0.467 M14 70 dimensionless 0.467 M15 90 dimensionless 0.600 M16 90 dimensionless 0.600

[0055] TABLE 2C Design of EECP for MS-DFF 83 RATIO Component EECP Unit of EECP R3 160 Ohm 1.000 R4 160 Ohm 1.000 R13 160 Ohm 1.000 R14 160 Ohm 1.000 L3 0 Picohenry 0.000 L4 0 Picohenry 0.000 L13 0 Picohenry 0.000 L14 0 Picohenry 0.000 K34 0 dimensionless 0.000 K134 0 dimensionless 0.000 MC1 240 dimensionless 1.500 MC11 240 dimensionless 1.500 M1 100 dimensionless 0.625 M2 100 dimensionless 0.625 M11 100 dimensionless 0.625 M12 100 dimensionless 0.625 M3 120 dimensionless 0.750 M4 120 dimensionless 0.750 M5 180 dimensionless 1.125 M6 180 dimensionless 1.125 M13 120 dimensionless 0.750 M14 120 dimensionless 0.750 M15 180 dimensionless 1.125 M16 180 dimensionless 1.125

[0056] Similarly, TABLE-2D summarizes a design overview of the BBPD 80 from the present invention. Notice that, among the three MS-DFF building blocks of MS-DFF 81, MS-DFF 82, and MS-DFF 83, the three columns of “RATIO of EECP” are all different and they are further graphically illustrated in FIG. 10. The corresponding output waveform of ΔPHASE is shown in FIG. 11. Again, except for a slight signal ripple 91, the output waveform exhibits near perfect performance for phase detection. TABLE 2D Overview of Design of EECP for BBPD 80 RATIO RATIO RATIO of EECP of EECP of EECP Component MS-DFF81 MS-DFF82 MS-DFF83 R3 1.000 1.000 1.000 R4 1.000 1.000 1.000 R13 1.000 1.000 1.000 R14 1.000 1.000 1.000 L3 4.667 3.333 0.000 L4 4.667 3.333 0.000 L13 4.667 3.333 0.000 L14 4.667 3.333 0.000 K34 0.003 0.003 0.000 K134 0.003 0.003 0.000 MC1 1.733 1.733 1.500 MC11 1.733 1.733 1.500 M1 1.333 1.333 0.625 M2 1.333 1.333 0.625 M11 1.333 1.333 0.625 M12 1.333 1.333 0.625 M3 0.600 0.467 0.750 M4 0.600 0.467 0.750 M5 0.467 0.600 1.125 M6 0.467 0.600 1.125 M13 0.600 0.467 0.750 M14 0.600 0.467 0.750 M15 0.467 0.600 1.125 M16 0.467 0.600 1.125

[0057] Thus, with the present invention, the quantitative design of all the passive and active circuit components of each building block of BBPD 80 is individually adjusted to achieve a high level of output signal quality in the presence of such deteriorating effects like output loading and interaction between functionally connected building blocks. Furthermore, these effects tend to become especially pronounced at high VCO frequencies such as those for high speed optical communications presented here.

[0058] As described with two exemplary cases, by systematically adjusting the EECP of all the passive and active circuit components of the individual building blocks of an electronic circuit system, one can achieve a high quality of output signal. This is especially important for applications with high clock frequency such as in optical communications where such effects of output loading and interaction between functionally connected building blocks tend to become highly pronounced. The invention has been described using exemplary preferred embodiments. However, for those skilled in this field, the preferred embodiments can be easily adapted and modified to suit additional applications without departing from the spirit and scope of this invention. For example, the present invention can be applied to a more generalized electronic circuit system using Field Effect Transistors (FET). As second advantage, the present invention can also be applied to an electronic circuit system using Bipolar transistors. As a third advantage, the methodology of circuit system design of the present invention, dealing with the minimization of systems level interaction effects amongst the various building blocks, is clearly independent of the particular geometry of the wafer process for the fabrication of the related IC, be it 0.25 μm, 0.18 μm or 0.09 μm. In fact, the methodology of the present invention is naturally scalable with the geometry of the wafer process as it continues its miniaturization process following the well known Moore's Law achieving a correspondingly higher speed of operation. Some of the related applications include, but without limitation to, Optical communication at 2.5 Gbit/sec (OC48), 10 Gbit/sec (OC192) and 40 Gbit/sec (OC768) data rate, Gigabit Ethernet, 10 Gigabit Ethernet, Blue Tooth technology (2.4 GHz) and wireless LAN (5.2 GHz). At such a high data rate, the hardware infrastructure for a multimedia information super highway is also enabled.

[0059] Thus, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements based upon the same operating principle. The scope of the claims, therefore, should be accorded the broadest interpretations so as to encompass all such modifications and similar arrangements. 

What is claimed are the following:
 1. An electronic circuit system for high speed signal processing comprising: a plurality of individually adjustable building blocks wherein each of the building blocks having a similar circuit topology that further comprises: a functionally interconnected set of passive components and a number of CMOS (Complementary Metal Oxide Semiconductor) transistors wherein each of said CMOS transistors is provided with an adjustable value of EECP (Electrically Equivalent Component Parameter), said EECP being further defined to be an Electrically Equivalent Channel Geometry (EECG) being equal to a ratio between a channel width and a channel length of the respective CMOS transistor; each of said passive components is provided with an adjustable value of EECP, said EECP being further defined to be a traditional component value of the respective passive component; and a vector quantity, called a Common Factor (CF), being defined as a vector ratio between the set of EECPs of said set of passive components and said number of CMOS transistors whereby each of the plurality of individually adjustable building blocks is adjusted in a manner so that the CF of each of the plurality of individually adjustable building blocks do not share an identical vector value to achieve a set of output signals with a set of desirable signal characteristics.
 2. The electronic circuit system for high speed signal processing according to claim 1 wherein the speed of signal processing is more than 10 Gbit/sec.
 3. The electronic circuit system according to claim 1 wherein the desirable signal characteristics of said set of output signals includes minimizing a deteriorating effect caused by interactions amongst two or more of the building blocks at the system level.
 4. The electronic circuit system according to claim 1 wherein the desirable signal characteristics of said set of output signals includes a reduction of the level of output signal ripple.
 5. The electronic circuit system according to claim 1 wherein the desirable signal characteristics of said set of output signals includes a reduction of the level of output signal jitter.
 6. The electronic circuit system according to claim 1 wherein the desirable signal characteristics of said set of output signals further includes a reduction of the level of unwanted output signal oscillation.
 7. The electronic circuit system according to claim 1 wherein the desirable signal characteristics of said set of output signals further includes increasing an output signal dynamic range.
 8. The electronic circuit system according to claim 1 wherein the desirable signal characteristics of said set of output signals further includes increasing an output signal linearity.
 9. The electronic circuit system according to claim 1 wherein the desirable signal characteristics of said set of output signals further includes increasing the accuracy of an output signal waveform.
 10. The electronic circuit system according to claim 1 wherein the desirable signal characteristics of said set of output signals further includes increasing the accuracy of an output signal phase angle.
 11. The electronic circuit system according to claim 1 wherein the electronic circuit system is specifically selected from the group consisting of flip-flops and dividers, registers and counters, timers, memories, Application Specific IC (ASIC), Arithmetic and Logic Units (ALU), embedded controllers, microprocessors, digital and analog filters, phase and frequency detectors, frequency synthesizers, multipliers and signal modulators, multiplexers and demultiplexers, phase-locked loops, data converters and multi-stage amplifiers.
 12. A method of designing an electronic circuit system for high speed signal processing, comprising the steps of: providing a plurality of individually adjustable building blocks wherein each of the building blocks has a similar circuit topology that further comprises a functionally interconnected set of passive components and a number of CMOS transistors; identifying, for each of said number of CMOS transistors, an adjustable value of EECP (Electrically Equivalent Component Parameter), said EECP being further defined to be an Electrically Equivalent Channel Geometry (EECG) being equal to a ratio between a channel width and a channel length of the respective CMOS transistor; identifying, for each of said passive components, an adjustable value of EECP, said EECP being further defined to be a traditional component value of the respective passive component; assigning a vector quantity, called a Common Factor (CF), being defined as a vector ratio between the set of EECPs of said set of passive components and said number of CMOS transistors; and adjusting each of the plurality of individually adjustable building blocks in a manner so that the CF of each of the plurality of individually adjustable building blocks do not share an identical vector value to achieve a set of output signals with a set of desirable signal characteristics.
 13. The method of designing an electronic circuit system according to claim 12 wherein the desirable signal characteristics of said set of output signals includes minimizing a deteriorating effect caused by interactions amongst two or more of the building blocks at the system level.
 14. The method of designing an electronic circuit system according to claim 12 wherein the desirable signal characteristics of said set of output signals includes a reduction of the level of output signal ripple.
 15. The method of designing an electronic circuit system according to claim 12 wherein the desirable signal characteristics of said set of output signals includes a reduction of the level of output signal jitter.
 16. The method of designing an electronic circuit system according to claim 12 wherein the desirable signal characteristics of said set of output signals further includes a reduction of the level of unwanted output signal oscillation.
 17. The method of designing an electronic circuit system according to claim 12 wherein the desirable signal characteristics of said set of output signals further includes increasing an output signal dynamic range.
 18. The method of designing an electronic circuit system according to claim 12 wherein the desirable signal characteristics of said set of output signals further includes increasing an output signal linearity.
 19. The method of designing an electronic circuit system according to claim 12 wherein the desirable signal characteristics of said set of output signals further includes increasing the accuracy of an output signal waveform.
 20. The method of designing an electronic circuit system according to claim 12 wherein the desirable signal characteristics of said set of output signals further includes increasing the accuracy of an output signal phase angle.
 21. The method of designing an electronic circuit system according to claim 12 wherein the electronic circuit system is specifically selected from the group consisting of flip-flops and dividers, registers and counters, timers, memories, Application Specific IC (ASIC), Arithmetic and Logic Units (ALU), embedded controllers, microprocessors, digital and analog filters, phase and frequency detectors, frequency synthesizers, multipliers and signal modulators, multiplexers and demultiplexers, phase-locked loops, data converters and multi-stage amplifiers. 